Pipelined Multipliers and FPGA Architectures

This paper studies pipelined multiplication techniques for implementation on FPGAs with emphasis on the utilisation of FPGA hardware resource. Performance of multiplier implementations are measured for commercially available FPGA architectures where two inherent issues are introduced and investigated. These being the imbalance of critical interconnect delay between general routing and static carry interconnects , and the amount of FPGA logic area used and its poor utilisation. For each of these issues suggestions are proposed and investigated.